Smp Cache 2.0 [WORK]
Smp Cache 2.0
The Specified-State Algorithm consists of two steps.
- The Specified-State, which is the first step in the algorithm, is carried out when a coherency cache transaction that transitions the cache from one state to another is considered. The Algorithm Specified-State is a method of converting a cache miss to a coherency transaction.
- The Update-to-the-Specified-State, which is the second step in the algorithm, is carried out when a coherency cache transaction that transitions the cache from one state to another is considered.
The cache snooping protocol, as described in CXL 2.0, includes the basic snooping logic that is used to allow caches to snoop for ownership on memory transactions. The CXL 2.0 cache snooping protocol is based on a second-level cache coherency protocol to achieve atomicity, can work in concert with DRAM transactions, and can be used to support memory buffers and address and data caches as well as instruction caches.
Chapter 5, “Snooping Protocols”. State is the state of a cache. There are two states for each cache: Valid and Invalid. Cache states can be monitored and set in the CXL 2.0 Cache Allocation Table, as shown in the figure below.
The rightmost column (owner) and rightmost row (victim) represent the states of the cache. The CXL 2.0 coherency algorithm builds upon the coherency mechanism of the CXL 1.0 and 1.1 specification. The Update-to-the-Specified-State Algorithm is shown in figure 2-9.
The Specified-State, as shown in figure 2-9, consists of two main phases. The cache state is checked, and if it is invalid, a coherency co-opercution, which is a TX of the cache line lock in CXL 2.0 is performed. Otherwise, the cache state is valid, and no coherency co-operation is performed. The Update-to-the-Specified-State, as shown in figure 2-11, consists of two main phases. The cache state is checked, and if it is valid, coherency co-operation is carried out for the cache line lock. Otherwise, the cache state is invalid, and the cache coherency co-operation is not performed.
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